1. Field of the Invention
The invention relates to the process of designing and fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus that facilitates minimum spacing and/or width control during an optical proximity correction process for a mask that is used in manufacturing an integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some other type of electromagnetic radiation together with suitably adapted masks and lithography equipment.
This light is reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem that arises during the optical lithography process is xe2x80x9cline end shorteningxe2x80x9d and xe2x80x9cpullbackxe2x80x9d. For example, the upper portion of FIG. 1 illustrates a design of a transistor with a polysilicon line 102, running from left to right, that forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. The lower portion of FIG. 1 illustrates a printed image that results from the design. Note that polysilicon line 102 has been narrowed using optical phase shifting in order to improve the performance of the transistor by reducing the resistance through the gate region.
Also note that because of optical effects and resist pullback there is a significant amount of line end shortening. This line end shortening is due to optical effects that cause the light to expose more of the resist under a line end than under other portions of the line.
In order to compensate for line end shortening, designers often add additional features, such as xe2x80x9chammer heads,xe2x80x9d onto line ends (see top portion of FIG. 2). The upper portion of FIG. 2 illustrates a transistor with a polysilicon line 202, running from left to right, which forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. A hammer head 204 is included on the end of polysilicon line 202 to compensate for the line end shortening. As is illustrated in the bottom portion of FIG. 2, these additional features can effectively compensate for line end shortening in some situations.
These additional features are typically added to a layout automatically during a process known as optical proximity correction (OPC). For example, FIG. 3 illustrates line end geometry 302 (solid line) prior to OPC and the resulting corrected line end geometry 304 after OPC (dashed line). Note that the corrected line end geometry 304 includes regions with a positive edge bias in which the size of the original geometry 302 is increased, as well as regions of negative edge bias in which the size of the original geometry 302 is decreased.
Unfortunately, the OPC process for a given edge typically does not take into account the amount of correction of neighboring edges, which can be located in the same feature or in different features. For example, a positive bias for a given edge can possibly cause a violation of a minimum spacing requirement between the given edge and an edge of a neighboring feature. In another example, a negative bias for a given edge can cause a violation of a minimum width requirement between the given edge and an opposing edge of the same geometric feature (see FIG. 9).
Undesirable effects caused by these interactions can be mitigated through a subsequent design rule checking (DRC) operation that takes place after the OPC process. However, this subsequent DRC operation takes place without the benefit of information that is available during the OPC process. Hence, modifications made by the subsequent DRC operation may adversely effect corrections made during the OPC process. For example, in FIG. 4A, an OPC process causes hammerheads 404 and 414 to be added to line ends 402 and 412, respectively. A subsequent DRC operation detects a minimum spacing violation between hammerheads 404 and 414, and corrects this violation by cutting away portions 406 and 416 from hammerheads 404 and 414. However, these corrections also adversely affect the optical proximity correction.
Undesirable effects caused by these interactions can also be mitigated during the OPC process. In some systems, when the OPC process detects a spacing constraint violation the OPC process simply stops and does not add an optical proximity correction or adds a scaled back optical proximity correction. For example, referring to FIG. 4B, the OPC process successfully places a hammerhead 404 on line 402. However, when the OPC process subsequently attempts to place a hammerhead on line end 412 a minimum spacing violation is detected, and no hammerhead is placed since there is not enough room for the correction. Note that this outcome results in an undesirable asymmetry between the resulting images of line ends 402 and 412.
What is needed is a method and an apparatus that facilitates minimum spacing and/or width control without adversely affecting corrections made by the optical proximity correction process.
One embodiment of the invention provides a system that facilitates minimum spacing and/or width control during an optical proximity correction operation for a layout of a mask used in manufacturing an integrated circuit. During operation, the system considers a target edge of a first feature on the mask and then identifies a set of interacting edges in proximity to the target edge. Next, the system performs the optical proximity correction operation, wherein performing the optical proximity correction operation involves applying a first edge bias to the target edge to compensate for optical effects in a resulting image of the target edge. While applying the first edge bias to the target edge, the system allocates an available bias between the first edge bias for the target edge and a second edge bias for at least one edge in the set of interacting edges.
In a variation on this embodiment, applying the first edge bias can involve adding a positive edge bias that increases the size of the first feature or adding a negative edge bias that decreases the size of the first feature.
In a variation on this embodiment, the second edge belongs to a second feature so that the distance between the target edge and the second edge defines a distance between the first feature and the second feature. In this variation, applying the first edge bias to the target edge involves satisfying a minimum spacing requirement between the target edge and the second edge. In a further variation, applying the first edge bias to the target edge additionally involves satisfying a minimum width requirement between the target edge and an opposing edge of the first feature.
In a variation on this embodiment, the second edge is also an edge of the first feature so that a distance between the target edge and the opposing edge defines a distance across a gap between portions of the first feature.
In a variation on this embodiment, the second edge is an opposing edge of the first feature so that a distance between the target edge and the opposing edge defines a width of the first feature. In this variation, applying the first edge bias to the target edge involves satisfying a minimum width requirement for the first feature between the target edge and the second edge.
In a variation on this embodiment, applying the first edge bias to the target edge involves considering an edge type of the target edge and considering an edge type of the second edge.
In a variation on this embodiment, allocating the available bias between the target edge and the second edge involves ensuring that the first edge bias of the target edge satisfies a minimum spacing requirement between the target edge and each edge in the set of interacting edges.
In a variation on this embodiment, allocating the available bias between the target edge and the second edge involves ensuring that the first edge bias of the target edge satisfies a minimum width requirement between the target edge and each edge in the set of interacting edges.
In a variation on this embodiment, the available bias is allocated based on relative weights assigned to the target edge and the second edge.
In a variation on this embodiment, allocating the available bias involves iteratively updating bias allocated to the target edge and the second edge in a manner that satisfies minimum spacing requirements or minimum width requirements.